Upgrade internal error message to external commit : 12e037e2090b1a6446376814ea0419463b02c254 author : Peter Eisentraut <peter@eisentraut.org> date : Mon, 24 Jun 2019 10:39:12 +0200 committer: Peter Eisentraut <peter@eisentraut.org> date : Mon, 24 Jun 2019 10:39:12 +0200 Click here for diff
As part of REINDEX CONCURRENTLY, this formerly internal-only error message becomes potentially user-visible (see regression tests), so change from errmsg_internal() to errmsg(), and update comment. M src/backend/catalog/index.c
Fix spinlock assembly code for MIPS so it works on MIPS r6. commit : 05399b14889e32f2714b428836c841b08d1d5258 author : Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 Click here for diff
Original MIPS-I processors didn't have the LL/SC instructions (nor any other userland synchronization primitive). If the build toolchain targets that ISA variant by default, as an astonishingly large fraction of MIPS platforms still do, the assembler won't take LL/SC without coercion in the form of a ".
Fix spinlock assembly code for MIPS so it works on MIPS r6. commit : 40dde829070ddebd3f8bbf06d8e1cc4bff2e0c06 author : Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 Click here for diff
Original MIPS-I processors didn't have the LL/SC instructions (nor any other userland synchronization primitive). If the build toolchain targets that ISA variant by default, as an astonishingly large fraction of MIPS platforms still do, the assembler won't take LL/SC without coercion in the form of a ".
Fix spinlock assembly code for MIPS so it works on MIPS r6. commit : 2854e2ab6806cc705d7ff92dd1f60f1cd70da98c author : Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 Click here for diff
Original MIPS-I processors didn't have the LL/SC instructions (nor any other userland synchronization primitive). If the build toolchain targets that ISA variant by default, as an astonishingly large fraction of MIPS platforms still do, the assembler won't take LL/SC without coercion in the form of a ".
Fix spinlock assembly code for MIPS so it works on MIPS r6. commit : 36d2c3ad33f8af9415e41b12822516a3e1e68486 author : Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 Click here for diff
Original MIPS-I processors didn't have the LL/SC instructions (nor any other userland synchronization primitive). If the build toolchain targets that ISA variant by default, as an astonishingly large fraction of MIPS platforms still do, the assembler won't take LL/SC without coercion in the form of a ".
Fix spinlock assembly code for MIPS so it works on MIPS r6. commit : 9895e3a36a72beec296a319c0462a1aa691ead53 author : Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Sat, 22 Jun 2019 20:31:50 -0400 Click here for diff
Original MIPS-I processors didn't have the LL/SC instructions (nor any other userland synchronization primitive). If the build toolchain targets that ISA variant by default, as an astonishingly large fraction of MIPS platforms still do, the assembler won't take LL/SC without coercion in the form of a ".
Fix archive retention expiring too aggressively. commit : 62715ebf2d8b0585c35cd2ee14d6aabf9cc0f1f8 author : Cynthia Shang <cynthia.shang@crunchydata.com> date : Wed, 19 Jun 2019 17:49:38 -0400 committer: David Steele <david@pgmasters.net> date : Wed, 19 Jun 2019 17:49:38 -0400 Click here for diff
The problem expressed when repo1-archive-retention-type was set to diff. In this case repo1-archive-retention ended up being effectively equal to one, which meant PITR recovery was only possible from the last backup.
Stamp 9.4.23. commit : a01e72fb69cb808364788b5360546f75cf2198df author : Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:26:08 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:26:08 -0400 Click here for diff
M configure
M configure.in
M doc/bug.template
M src/include/pg_config.h.win32
M src/interfaces/libpq/libpq.rc.in
M src/port/win32ver.rc
Translation updates commit : 5eaeea2cecb98161d41e11aff917c91177a8ad0c author : Peter Eisentraut <peter@eisentraut.org> date : Mon, 17 Jun 2019 14:45:16 +0200 committer: Peter Eisentraut <peter@eisentraut.
Stamp 9.5.18. commit : 683c768cbb7adc18fa0be93e41a090a48b000225 author : Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:23:53 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:23:53 -0400 Click here for diff
M configure
M configure.in
M doc/bug.template
M src/include/pg_config.h.win32
M src/interfaces/libpq/libpq.rc.in
M src/port/win32ver.rc
Translation updates commit : 944bf6b4df7d005de130e4d1c3a735788f89e5c3 author : Peter Eisentraut <peter@eisentraut.org> date : Mon, 17 Jun 2019 14:46:50 +0200 committer: Peter Eisentraut <peter@eisentraut.
Stamp 9.6.14. commit : 25cd1175fce691517c9e55311d9a1e4ecf930a32 author : Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:21:22 -0400 committer: Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 17:21:22 -0400 Click here for diff
M configure
M configure.in
M doc/bug.template
M src/include/pg_config.h.win32
M src/interfaces/libpq/libpq.rc.in
M src/port/win32ver.rc
Last-minute updates for release notes. commit : 7dc3e28173b6d7527a24bb8a4e324137c7cfe9d2 author : Tom Lane <tgl@sss.pgh.pa.us> date : Mon, 17 Jun 2019 10:53:45 -0400 committer: Tom Lane <tgl@sss.